The present invention relates to electroplating and electroless plating of conductive materials into openings. In some embodiments, the plated materials are used to form through hole interconnects in integrated circuits.
Fabrication of through hole interconnects in integrated circuits using electroplating has been described in U.S. Pat. No. 6,184,060 issued Feb. 6, 2001 to Siniaguine, and is illustrated in FIGS. 1 and 2. Wafer 104 includes a silicon substrate 110. The wafer has a face side 104F and a back side 104B. Openings 114 are etched in substrate 110 in the face side 104F. Dielectric 120 is deposited in the openings by chemical vapor deposition (CVD) or thermal oxidation. Metal 130 is sputtered on dielectric 120. Metal 140 is electrodeposited (electroplated) to fill up the openings.
Then the wafer is thinned by an etch of the back side 104B (FIG. 2). Dielectric 120 is exposed and attacked by the etch, and metal 130 becomes exposed. The exposed metal 130 provides backside contact pads that can be attached to another integrated circuit. Metal 140 increases the mechanical strength of the structure and improves heat dissipation.